Along with the progress in semiconductor technology, to increase the integrity of semiconductor devices and to satisfy the demand of high device performance, the chip stacking technology has been developed rapidly. Particularly, the through-silicon-via (TSV) technology is deemed as a new-generation interconnect applied in the three-dimensional (3D) integrated circuit (IC) technology.
The TSV technology applied in the 3D stacking of ICs is, for example, forming a hole with a high aspect ratio in a first surface (front side) of a substrate of chip first, and then filling a conductive material into the hole. Then, a chemical/mechanical polishing process is performed to remove the conductive material outside the hole. Then, a portion of a second surface (back side) of the substrate is removed to thin the substrate and expose the conductive material in the hole. Next, a plurality of chips are bonded together by stacking, and the chips are electrically connected through the conductive material in the hole.
Since in the TSV technology, the substrate of the chips is penetrated, the stacked chips are able to transmit signals to one another. Such approach is different from the traditional circuit layout technology in which circuit devices are manufactured on a substrate surface. Therefore, the TSV technology also produces many new problems to be solved, such as how to control a metal oxide semiconductor (MOS) capacitance device that appears together with a conductive via precisely, how to reduce the signal coupling between two adjacent conductive vias, and how to eliminate the noise in the substrate.